Graphcore

In a genomics research cluster, a drug discovery model is running on a molecular interaction graph with 400 million nodes. On a GPU cluster, the same computation takes 14 hours. On Graphcore’s IPU-POD256, it completes in 38 minutes, not because the software is optimized differently, but because the processor holds the entire model inside the chip, eliminating the memory transfers that consume the majority of GPU compute cycles. This is the architectural difference that Graphcore has built since 2016, and it is the reason the company has earned a 2026 Global Recognition Award. The Bristol-founded semiconductor company, now a wholly owned subsidiary of SoftBank Group and builder of the world’s first 3D wafer-on-wafer commercial AI processor, has validated a decade-long thesis that the path to next-generation AI compute runs through a fundamentally different processor architecture, not an incremental improvement on the GPU.

Technical Innovation and Architecture

Graphcore’s Intelligence Processing Unit stores the complete machine learning model within the processor via its In-Processor-Memory architecture, eliminating the off-chip memory access cycle, which is the primary performance constraint in GPU-based AI workloads. The Colossus MK2 GC200 IPU, built on TSMC’s 7nm process with 59.4 billion transistors, runs 1,472 independent processor cores executing nearly 9,000 parallel program threads simultaneously, delivering 250 teraFLOPS of AI compute with memory bandwidth exceeding 45TB/s, more than 20 times the bandwidth available from Nvidia’s A100 HBM architecture. This bandwidth differential is not marginal; for Graph Neural Networks, sparse transformers, and Bayesian inference workloads, where the majority of memory accesses involve small, irregular data structures that off-chip HBM serves inefficiently, the IPU’s in-processor bandwidth translates directly into order-of-magnitude throughput improvements.

The Bow IPU, Graphcore’s current-generation processor, is the world’s first commercial chip built using 3D wafer-on-wafer silicon stacking: a dedicated power delivery wafer stacked beneath the compute wafer at the silicon level, not the package level. This architecture achieves 350 teraFLOPS of AI compute, 65TB/s of memory bandwidth, and 16% better power efficiency with 40% higher performance versus the prior generation — all within a chip that fits in the same physical form factor and thermal envelope as its predecessor. Up to 64,000 Bow IPUs connect through Graphcore’s proprietary IPU-Fabric interconnect to form petaFLOP-scale AI compute clusters without third-party networking infrastructure. The Poplar SDK maps PyTorch, TensorFlow, ONNX, and JAX workloads onto the IPU architecture with native sparsity support, delivering up to 10x throughput gains for sparse AI computations, where GPU dense computation wastes cycles on zero-value operations.

Market Strategy and Leadership

Co-Founders Nigel Toon (Electrical Engineering, Imperial College London) and Simon Knowles bring a combined track record of two prior semiconductor company exits — Icera to Nvidia for $435 million in 2011, and Element 14 to Broadcom for $640 million in 2000 — to the IPU venture. The irony that the founders built and sold the company that became Graphcore’s primary market competitor directly informs the architectural decisions behind the IPU: both founders understood exactly where Nvidia’s GPU architecture leaves performance on the table for AI workloads, and both had the semiconductor design experience to build an alternative. Graphcore raised $682 million from 34 investors, including Sequoia Capital, Microsoft, Ontario Teachers’ Pension Plan, Fidelity International, and Baillie Gifford, reaching a peak valuation of $2.77 billion in December 2020 before SoftBank Group completed its acquisition in July 2024.

Under SoftBank ownership, Graphcore’s go-to-market model shifted from independent enterprise hardware sales to integration within SoftBank’s Artificial Super Intelligence infrastructure platform. The next-generation Izanagi chip, combining IPU parallel processing with Ampere ARM server CPU architecture, targets deployment across Stargate hyperscale data centers in the United States and Japan in 2026 — a distribution scale achievable only through SoftBank’s capital and infrastructure relationships. The October 2025 announcement of a £1 billion investment in a new AI Engineering Campus in Bengaluru, India, creating 500 semiconductor engineering roles across logical design, physical design, verification, and chip bring-up functions, confirms that SoftBank treats Graphcore as a long-term semiconductor R&D platform rather than a financial portfolio asset awaiting disposal.

Industry Impact and Future Vision

Graphcore’s IPU architecture has enabled research and commercial applications that GPU memory bandwidth constraints made impractical at production scale: genomics organizations running molecular interaction graph simulations at minutes rather than hours; pharmaceutical research teams accelerating drug candidate screening through IPU-powered molecular dynamics; financial institutions executing Bayesian inference models for risk computation at latencies incompatible with GPU batch processing requirements; and scientific computing programs at CERN and Cambridge using IPU-accessible free research allocations to run graph-based physics simulations. The native sparsity support in IPU hardware aligns with the direction of AI model architecture development. As researchers build sparser, more efficient models to reduce training and inference costs, the IPU’s advantage over dense GPU computation increases rather than diminishes.

The Izanagi chip roadmap, the Bengaluru Engineering Campus scaling toward 500 semiconductor engineers, and integration within SoftBank’s Stargate deployment pipeline collectively position Graphcore’s next hardware generation as the AI accelerator inside the world’s highest-profile hyperscale AI infrastructure build-out of 2026. The academic ecosystem program — free IPU access for university research and active scientific collaborations — builds the developer community and research validation pipeline that ensures the IPU architecture evolves in direct response to the frontier of AI model development. For commercializing the world’s first in-processor-memory AI accelerator, the world’s first 3D wafer-on-wafer production processor, and the first architecturally coherent alternative to GPU dominance in AI compute, Graphcore has fully earned the distinction of the 2026 Global Recognition Award.